1. Field
The present invention relates to a non-volatile semiconductor storage device.
2. Description of the Related Art
NAND-cell type flash memory has a sense amplifier circuit that determines data by detecting the absence or presence, or the magnitude of cell currents flowing depending upon data of memory cells. A sense amplifier circuit is usually connected to a bit line to which many memory cells are connected. Sense amplifiers include voltage detection type sense amplifiers and current detection type sense amplifiers.
In the voltage detection type sense amplifiers, for example, a bit line separated from a memory cell is precharged to a certain voltage, and then discharged by a selected memory cell. The discharged state of the bit line is detected by a sense node connected to the bit line. In data sensing, a bit line should be separated from a current source load to detect a bit-line voltage that is determined by data (cell data) retained in a memory cell (see, for example, Japanese Patent Laid-Open No. 2000-076882).
On the other hand, the current detection type sense amplifiers perform data sensing with supplying a read current from a current source load via a bit line to a memory cell. The magnitude of a current flow depends on the cell data, and thus the voltages of the bit line and a sense node connected to the bit line vary with cell data. Data is determined by detecting this voltage difference of the sense node (see, for example, Japanese Patent Laid-Open No. 2006-79803).
The voltage detection type sense amplifiers consume less power since they determine cell data by means of charging and discharging of electric charge of a bit line. However, due to large capacity memory with a large bit-line capacitance, it takes a longer time to charge or discharge the bit line, and thus it becomes more difficult to achieve high-speed sensing. In addition, in a voltage detection type sense amplifier, the bit line voltage may swing relatively larger depending on cell data. Accordingly, coupling noise between adjacent bit lines is problematic. As such, it is necessary to employ a bit line shield scheme in which an odd-numbered bit line is used as a shield line when an even-numbered bit line is sensed. Therefore, it is not possible to sense neighboring bit lines concurrently if the voltage detection type sense amplifiers are used.
In contrast, the current detection type sense amplifiers allow for high-speed sensing since they perform data sensing while supplying a read current via a bit line to a memory cell. In addition, a clamping transistor positioned between a bit line and a sense node may reduce the swing of bit-line voltage depending on cell data, and thus coupling noise between neighboring bit lines is not a significant problem. Therefore, such NAND-cell type flash memory employing a scheme to read a plurality of adjacent bit lines concurrently (All Bit Line sense scheme: ABL sense scheme) utilize the current detection type sense amplifiers.
However, these current detection type sense amplifiers suffer from increased power consumption due to continuous supply of a read current from a current load source. Particularly, problems arise when all bit lines are read concurrently in the ABL scheme: the charging time becomes longer because of increased parasitic capacitance of bit lines due to miniaturization of memory cells, increasing the current consumption as well as sensing times.
Therefore, as described in Japanese Patent Laid-Open No. 2006-79803, after reading all bit lines in the first read operation with the ABL scheme, supply of a read current from a current source load is ceased in the second read operation for those bit lines from which “1” data has already been read in the first read operation. This scheme may suppress current consumption.
However, the above-mentioned scheme also has a problem in that the read current has a large peak value and the peak current period increases since all bit lines are to be read in the first read operation. Notably, since the spacing between adjacent bit lines becomes smaller and smaller as miniaturization of memory cells advances, the parasitic capacitance of bit lines increases correspondingly and it takes longer for the bit lines to be charged to a certain voltage.